Top "Vlsi" questions

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single chip.

How to sign-extend a number in Verilog

I'm working on a simple sign-extender in Verilog for a processor I'm creating for Computer Architecture. Here's what I've got …

verilog vlsi
test bench for writing verilog output to a text file

i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while …

verilog vlsi
Verilog: how to take the absolute value

In verilog I have an array of binary values. How do I take the absolute value of the subtracted values ? …

verilog hdl vlsi
$display vs $strobe vs $monitor in verilog?

What is the difference between $display vs $strobe vs $monitor in verilog? When in the event queue does each apply, …

verilog vlsi register-transfer-level
Better way of coding a RAM in Verilog

Which code is better in writing a RAM? assigning data_out inside always block: module memory( output reg [7:0] data_out, …

verilog vlsi
How to use clock gating in RTL?

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place &…

verilog system-verilog register-transfer-level vlsi
Shift Registers Verilog

I am very new to HDL language. I have a question about how to program a shift register. (i know …

verilog vlsi
malformed statement in verilog

Hi i am using the folowing code to design a n-bit counter. Depending on the start and end i want …

verilog system-verilog vlsi
Verilog FIFO code written with different styles..one not working and another not working.Can someone explain

I have written verilog code for fifo using fillcount to check as the means for checking if it is full …

verilog fifo vlsi
System Verilog always_latch vs. always_ff

Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch. The former …

system-verilog vlsi register-transfer-level