Better way of coding a RAM in Verilog

e19293001 picture e19293001 · Oct 3, 2011 · Viewed 29k times · Source

Which code is better in writing a RAM?

  1. assigning data_out inside always block:

    module memory(
        output reg [7:0] data_out,
        input [7:0] address,
        input [7:0] data_in, 
        input write_enable,
        input clk
    );
        reg [7:0] memory [0:255];
    
        always @(posedge clk) begin
            if (write_enable) begin
                memory[address] <= data_in;
            end
            data_out <= memory[address];
        end
    
    endmodule
    
  2. assigning data_out using assign statement:

    module memory(
        output [7:0] data_out,
        input [7:0] address,
        input [7:0] data_in, 
        input write_enable,
        input clk
    );
        reg [7:0] memory [0:255];
    
        always @(posedge clk) begin
            if (write_enable) begin
                memory[address] <= data_in;
            end
        end
    
        assign data_out = memory[address];
    
    endmodule
    

Any recommendations?

Answer

toolic picture toolic · Oct 3, 2011

It depends on your requirements.

  1. This registers your memory output. If you are synthesizing this to gates, you will have 16 more flip-flops than in case 2. That means you use a little more area. It also means your output will have less propagation delay relative to the clock than case 2. Furthermore, the output data will not be available until the next clock cycle.

  2. Your output data will be available within the same clock cycle as it was written, albeit with longer propagation delay relative to the clock.

You need to decide which to use based on your requirements.

A third option is to use a generated RAM, which is a hard macro. This should have area, power and possibly timing advantages over both case 1 and 2.