System Verilog always_latch vs. always_ff

Question

Just started learning System Verilog. I am confused about the usage of statements always_ff and always_latch. The former would be used as:

always_ff @ (posedge clk)
begin
    a <= b;
end

while the latter:

always_latch
begin
    a <= b;
end

The first is activated just by the positive edge of the clock and coupled with non-blocking assignment produces a FF.

The always_latch is obviously thought to represent a latch, but then why use a non-blocking assignment? Wouldn't be better using a always_comb with blocking assignments?

Answer 1

By using always_latch or always_ff a designers intent to infer a latch or a sequential logic respectively, but if the logic is not correct software tools can warn the designer that the intended hardware logic is not inferred properly.

eg:

always_ff @ (posedge clk or negedge rst) 
begin
  if (!rst)
    a <= '0;
end

For the above code the designer intended to get only a sequential logic and not a latch but a latch would be generated in actual (Any static tool will generate a warning message as "Latch will be inferred for the logic")

Similarly for the below code the designers intent is to infer a hardware latch so tool will(understand your logic better) and won't report it.

    always_latch
    begin
      if (rst)
        a <= b;
    end

Latch is a sequential logic which works on levels of clocks instead of clock edges.

In general best practice is to use Non-blocking assignments for sequential logic and blocking assignments for combinatorial logic which is explained in detail under Section 5.0 Verilog coding guidelines of Nonblocking Assignments in Verilog Synthesis, Coding Styles That Kill!

Guideline #2: When modeling latches, use nonblocking assignments.