Top "Verilog" questions

How to use clock gating in RTL?

I am clock gating some latch and logic in my design. I don't have much experience in synthesis and place &…

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What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)

What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more …

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Difference between Behavioral, RTL and gate Level

I'm trying to fully understand the differences between the abstraction levels of Verilog, I get what the description of each …

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How do I read an environment variable in Verilog/System Verilog?

How do I read an environment variable in Verilog ? (Running on a VCS simulator) I am trying to accomplish File=$…

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Compilation error: A net is not a legal lvalue in this context

I am a newbie to Verilog and had a problem while defining a if-else loop. The error message is A …

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How to interface a vga monitor to fpga using verilog?

I am using virtex - 5 fpga board and i am new in working with fpga board please suggest me any …

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Shift Registers Verilog

I am very new to HDL language. I have a question about how to program a shift register. (i know …

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What to use to compile and simulate Verilog programs on Mac OS X 10.6.8?

I am required to simulate Verilog programs as part of my syllabus. But, my college uses Xilinx ISE, and it …

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Seven Segment Multiplexing on Basys2

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four …

verilog fpga hdl synthesis multiplexing

What's the best way to tell if a bus contains a single x in verilog?

I have a test bench that monitors a bus. Some of signals within the bus can be 1'bx. For a …

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