What's the best way to tell if a bus contains a single x in verilog?

verilog system-verilog
Doov picture Doov · Jul 1, 2013 · Viewed 17.2k times · Source

I have a test bench that monitors a bus. Some of signals within the bus can be 1'bx. For a variety of reasons I need to know if any of the signals within the bus are 1'bx. What's the best way to test (not for synthesis -- only for simulation purposes) if a bus contains any x's? I had hoped that I could use a reduction or and then use ===, but this doesn't seem to work. Thanks,

D

Answer

toolic picture toolic · Jul 1, 2013

You can use $isunknown (refer to the IEEE Std 1800-2017, section 20.9 Bit vector system functions):

module tb;

reg [3:0] data;

initial begin
    #5 data = 4'b0101;
    #5 data = 4'b000x;
    #5 data = 4'b1111;
    #5 data = 4'b0x0x;
    #5 data = 4'b0x1x;
    #5 data = 4'bzzzz;
    #5 $finish;
end

always @(data) begin
    if ($isunknown(data)) $display($time, " data=%b has x's", data);
end

endmodule

Outputs:

                  10 data=000x has x's
                  20 data=0x0x has x's
                  25 data=0x1x has x's
                  30 data=zzzz has x's

Note that this also treats z as x.

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