Design 32 bit arithmetic logic unit (ALU)

verilog alu
maryam picture maryam · May 20, 2015 · Viewed 10.3k times · Source

I write this coder for an ALU. This ALU controlled with ctrl signals and do some works like add, subtract, and, or, ... When output is zero, oZero signals should be active.

I have some errors in marked lines. What is my mistake?

module ALU_32 (iA, iB ,iCin ,ctrl, oCarry,oZero, out);    
input [31:0] iA,iB;
output [31:0] out;
input iCin,ctrl;
output oCarry,oZero;
reg [31:0] out;
reg oCarry;
reg oZero;
always@ (ctrl)
    begin 
        case(ctrl)
            4'b0: out<=iA&iB;
            4'b0001: out<=iA|iB;
            4'b0010: {oCarry ,out}<=iA+iB;
            4'b0011: out<=iA~|iB;    //error
            4'b0100: 
            begin 
                if(iA==iB)
                    out<=32'b1;
            end  
            4'b0101: out<=iA-iB;  //error
            4'b0110:    //error
            begin 
                if(iA<iB)
                    out<=32'b1;
                else
                    out<=32'b0;
                end
            4'b0111:   out<=iA*iB;     //error
            4'b1000: out<=iA/iB;        //error

        end
       always@(out)
           begin
               if(out==0)
                   oZero<=1;
               end

      endmodule

Answer

Qiu picture Qiu · May 20, 2015

~| operator that you used in 4'b0011: out<=iA~|iB; is treated by your IDE as a reduction operator and not as a NOR operation. To fix that you can use e.g. following construct:

out <= ~(iA | iB);

Second problem is that you forgot to use endcase keyword at the end of your case construct.

Check edaplayground to see those changes applied to your code.

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