Verilog linting tools?

verilog lint typechecking hdl
mrflibble picture mrflibble · Jan 30, 2011 · Viewed 11.2k times · Source

What are some good linting tools for verilog? I'd prefer one that can be configured to either handle or ignore certain vendor specific primitives like LUT's, PLL's, etc.

I recently tried verilator-3.810, but out of the box it needs a little help with the primitives.

So what (linting) tools do you use to deal with the not-so-strict syntax of verilog?

Answer

toolic picture toolic · Jan 30, 2011

I have never used a free linting tool, such as the one you mentioned (verilator).

My only experience has been with (expensive) commercial linting tools. Thus far, every one I have used has required me to spend time to customize the rule-set to filter out checks which I consider unimportant. For example, by default, every tool generates many warnings related to signal naming conventions. Since these in no way affect how RTL is synthesized to gates or lead to simulation issues, I choose to disable them.

The Spyglass tool (Atrenta) seems to have the widest range of capabilities, but also requires quite a bit of set-up. I like the Hal tool (Cadence) because it is very easy to start using right away (but, it too requires some set-up).

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