inout with reg type in verilog

verilog inout
Priya Mittal picture Priya Mittal · Jun 12, 2018 · Viewed 8.5k times · Source

I have used inout with c, but for c to be on the LHS of procedural assignment, it needs to be a reg type variable. Can anyone help me out with this code?

module multiedgeclk(input clk ,[7:0] a,b,d, inout [7:0] c, output reg [7:0]f); 
     always @(posedge clk)
          c <= a + b;
     always @(negedge clk)
          f = c & d;
endmodule

Answer

Eddy Yau picture Eddy Yau · Jun 12, 2018

In verilog inout is the direction of the port. wire or reg is the type of the signal. If you want to drive a bi-directional port, it should be declare as inout wire or inout and drive it with enable signal Here is a example of bi-directional port.

module ABC( inout [7:0] c );
reg [7:0] c_out;
reg out_en;
assign c = out_en ? 8'hz : c_out; 
/* something here
... 
*/
endmodule

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