Top "Verilog" questions

Verilog is a hardware description language (HDL) used to model electronic systems.

How does Verilog behave with negative numbers?

For instance, say I have a reg [7:0] myReg I assign it the value -8'D69 I know Verilog stores it …

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verilog negative-number
ADDRESS WIDTH from RAM DEPTH

I am implementing a configurable DPRAM where RAM DEPTH is the parameter. How to determine ADDRESS WIDTH from RAM DEPTH? …

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verilog system-verilog
test bench for writing verilog output to a text file

i am unable to get correct output in a text file however simulation in modelsim is quite ok.. but while …

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verilog vlsi
Assign integer to reg in Verilog

I have problems with this Verilog code. Basically, it won't let me do the Y = 3'di statement. Basically, I want …

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verilog
If statement and assigning wires in Verilog

I am trying to figure out the basics of assigning wires based on combinational logic. I have: wire val; wire …

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logic hardware verilog hdl
Verilog Always block using (*) symbol

I have a simple question regarding how to write an always block in a Verilog module. If I have the …

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verilog
What is the difference between = and <= in Verilog?

What is the difference between = and <= in this code? Also, how do I print the value of data? module …

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verilog
What is the difference between Verilog ! and ~?

So it ended up that the bug that had kept me on for days, was a section of code that …

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verilog boolean-logic modelsim
What is the difference between structural Verilog and behavioural Verilog?

As in the title, what are the main differences between structural and behavioural Verilog?

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verilog
Instantiate Modules in Generate For Loop in Verilog

I'm trying to instantiate some modules in Verilog using a generate block since I'm going to be instantiating a variable …

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verilog system-verilog