What is the difference between = and <= in Verilog?

verilog
Hayder Al-Amily picture Hayder Al-Amily · Feb 16, 2016 · Viewed 44.6k times · Source

What is the difference between = and <= in this code? Also, how do I print the value of data?

    module always_example();
reg clk,reset,enable,q_in,data;

always @ (posedge clk)
if (reset)  begin
   data <= 0;
end else if (enable) begin   
   data <= q_in;
end
// if i put     $print("data=%d", data);   there is error
endmodule

Answer

Sourabh picture Sourabh · Feb 17, 2016

= is blocking statement. In an always block, the line of code will be executed only after it's previous line has executed. Hence, they happens one after the other, just like combinatoral logics in loop.

<= is non-blocking in nature. This means that in an always block, every line will be executed in parallel. Hence leading to implementation of sequential elements.

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