Assign integer to reg in Verilog

verilog
DemonicImpact picture DemonicImpact · Oct 17, 2010 · Viewed 47.7k times · Source

I have problems with this Verilog code. Basically, it won't let me do the Y = 3'di statement. Basically, I want Y to equal i. I am pretty sure the problem is the i. So, is there a way to do this in Verilog? Also, W is an input with 8 bits (in other words, W[7:0]). 

for (i = 7; i >= 0; i = i - 1)
begin
    if(W[i]) Y=3'di;
end

Thanks.

Answer

Jeff Mercado picture Jeff Mercado · Oct 17, 2010

You can select bits using brackets .

for (i = 7; i >= 0; i = i - 1)
begin
    if(W[i]) Y = i[2:0];
end

But it isn't even necessary if i was declared to be an integer. It will take however many bits fit in Y automatically and you only wanted the LSBs.

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