What is the difference between structural Verilog and behavioural Verilog?

verilog
user2219586 picture user2219586 · Mar 28, 2013 · Viewed 43.3k times · Source

As in the title, what are the main differences between structural and behavioural Verilog?

Answer

toolic picture toolic · Mar 28, 2013

There is no strict definition of these terms, according to the IEEE Std. However, customarily, structural refers to describing a design using module instances (especially for the lower-level building blocks such as AND gates and flip-flops), whereas behavioral refers to describing a design using always blocks.

Gate netlists are always structural, and RTL code is typically behavioral. It is common for RTL to have instances of clock gates and synchronizer cells.

Related questions

How to declare and use 1D and 2D byte arrays in Verilog?

How to declare and use 1D and 2D byte arrays in Verilog? eg. how to do something like byte a_2D[3][3]; byte a_1D[3]; // using 1D for (int i=0; i< 3; i++) { a_1D[i] = (byte)i; } // using 2D for (…

Read More
Verilog: How to instantiate a module

If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top? top: module top( input clk, input rst_n, input enable, input [9:0] data_rx_1, input [9:0] data_rx_2, output [9:0] data_tx_2 ); subcomponent: module …

Read More
Using wire or reg with input or output in Verilog

When you declare something as input or output, how do you know if you have to also declare it as a reg or a wire?

Read More