Top "Hdl" questions

Declaring an array within an entity in VHDL

I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design. I need a way …

syntax-error vhdl hdl

Incrementing Multiple Genvars in Verilog Generate Statement

I'm trying to create a multi-stage comparator in verilog and I can't figure out how to increment multiple genvars in …

hardware syntax-error verilog system-verilog hdl

"component instance "uut" is not bound" when simulating test bench with GHDL simulator

I am having a problem with using GHDL (http://ghdl.readthedocs.io/en/latest/) to simulate my VHDL design. So, …

vhdl fpga hdl ghdl

Verilog linting tools?

What are some good linting tools for verilog? I'd prefer one that can be configured to either handle or ignore …

verilog lint typechecking hdl

How do I set output flags for ALU in "Nand to Tetris" course?

Although I tagged this homework, it is actually for a course which I am doing on my own for free. …

hdl alu nand2tetris

Calculations with Real Numbers, Verilog HDL

I noticed that Verilog rounds my real number results into integer results. For example when I look at simulator, it …

numbers verilog hdl real-datatype

Always vs forever in Verilog HDL

What are the difference between the always keyword (not the always @ block) and forever keyword in Verilog HDL? always #1 a=!…

verilog hdl icarus

how do i initialize a std_logic_vector in VHDL?

i have a std_logic_vector(4096 downto 0) Signal and i want to initialize it like below: architecture Behavioral of test …

vhdl hdl xilinx-ise

Verilog, Parallel in Series out Shift Register

I am learning and practicing Verilog HDL. I wanted to design a 16 bit parallel in series out shift register. module …

verilog hdl shift-register

Signal is connected to following multiple drivers

I trying to run the following and I receive this error: Here's the Verilog code: module needle( input referrence,input …

compiler-errors verilog xilinx hdl