Verilog, Parallel in Series out Shift Register

Question

I am learning and practicing Verilog HDL. I wanted to design a 16 bit parallel in series out shift register.

module verilog_shift_register_test_PISO( din, clk, load, dout );

output reg dout ;

input [15:0] din ;
input clk ;
input load ;

reg [15:0]temp;

always @ (clk or load) begin
 if (load)
  temp <= din;
 else begin
  dout <= temp[0];
  temp <= {1'b0, temp[15:1]};
 end
end
endmodule  

I wrote this code and tried to simulate it.

simulation result

simulation_result I could not understand the reason why data output (dout) signal is always LOW

Answer 1

It works for me.

BUT!
That code can no be turned into gates. You must use 'posedge clk' or 'negedge clk'. Also your load is a-synchronous which is very unusual and can give race conditions against the clock edge.

always @ (posedge clk)
begin
   if (load)
      temp <= din;
   else
   begin
     dout <= temp[0];
     temp <= {1'b0, temp[15:1]};
   end
end

Furthermore it is usual to have a reset condition. As long as there is no 'load' signal the dout will produce X-es. This can very much upset the rest of your circuit. Also you have an extra clock delay in dout. You could, if you want, save a clock cycle there. Here its is with an a-synchronous active low reset:

always @ (posedge clk or negedge reset_n)
begin
   if (!reset_n)
      temp <= 16'h0000;
   else
   if (load)
      temp <= din;
   else
     temp <= {1'b0, temp[15:1]};
end

assign dout = temp[0];