Signal is connected to following multiple drivers

Question

I trying to run the following and I receive this error:

Here's the Verilog code:

module needle( input referrence,input  penalty,output index[7:0]);
//inout input_itemsets;
//input referrence;

//input penalty;
//output index;
parameter max_cols=8;
//
wire index[7:0];
wire referrence;
wire penalty;
//wire input_itemsets;
genvar i,idx;
generate
for( i = max_cols-4 ; i >= 0 ; i=i-1)
    for( idx = 0 ; idx <= i ; idx=idx+1)
        begin
             assign index[i] = (idx + 1) * max_cols + (i + 1 - idx);
             //assign index = (idx + 1) * max_cols + (i + 1 - idx);
            //input_itemsets[index] <= maximum( input_itemsets[index-1-max_cols]+ referrence[index],
            //input_itemsets[index-1] - penalty,
            //input_itemsets[index-max_cols] - penalty);

        end
   endgenerate

endmodule

and here's the warnings and errors I receive:

WARNING:HDLCompiler:413 - "/home/suriyha/Monajalal/needle_t1/needle.v" Line 39: Result of 4-bit expression is truncated to fit in 1-bit target.
ERROR:HDLCompiler:1401 - "/home/suriyha/Monajalal/needle_t1/needle.v" Line 39: Signal  index[3] in unit needle is connected to following multiple drivers:
Driver 0: output signal of instance Power (PWR_1_o_BUF_9).
Driver 1: output signal of instance Ground (GND_1_o_BUF_8).
Driver 2: output signal of instance Ground (GND_1_o_BUF_6).
Driver 3: output signal of instance Ground (GND_1_o_BUF_4).
Driver 4: output signal of instance Ground (GND_1_o_BUF_11).
Module needle remains a blackbox, due to errors in its contents
WARNING:HDLCompiler:1499 - "/home/suriyha/Monajalal/needle_t1/needle.v" Line 21: Empty module <needle> remains a black box.

However the main code is "assign index = (idx + 1) * max_cols + (i + 1 - idx);" but I decided to make "index" an array to avoid this problem, however I am yet running to it. So no matter if index is an array or just a variable I yet have this multiple value problem.

Also the C version of the code is :

for( idx = 0 ; idx <= i ; idx++){
    index = (idx + 1) * max_cols + (i + 1 - idx);
    input_itemsets[index]= maximum( input_itemsets[index-1-max_cols]+ referrence[index],
    input_itemsets[index-1] - penalty,
     input_itemsets[index-max_cols] - penalty);
 }

I would also like to know if we can have a nested loop like what we have in its C counter part in the Verilog version or how to avoid the "multiple driver" problem in this case??

Thanks.

Answer 1

In your Verilog code, most index bits are constants that are either double driven(x) or not driven(z): index[7:0]:zzzxxxx1

The explanation is the following. The outer loop is from 4 to 0, which means index[7:5] are undriven(z). The inner loop is from 0 to i, which unrolls to something like the following:

assign index[4] = (0 + 1) * max_cols + (4 + 1 - 0);
assign index[4] = (1 + 1) * max_cols + (4 + 1 - 1);
...
assign index[1] = (0 + 1) * max_cols + (1 + 1 - 0);
assign index[1] = (1 + 1) * max_cols + (1 + 1 - 1);
assign index[0] = (0 + 1) * max_cols + (0 + 1 - 0);

So index[4:1] are double driven(x), and only index[0] has a single driver.

Compiled code with a test here: EDA Playground