I'm trying to make a buffer to hold 16, 16-bit wide instructions for a small CPU design.
I need a way to load instructions into the buffer from my testbench. So I wanted to use an array of std_logic_vectors to accomplish this. However, I am getting a syntax error and I'm not sure why (or if I'm allowed to do this in VHDL for that matter).
The syntax error is at the line where I declare instructions
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
entity instruction_buffer is
port
(
reset : in std_logic;
instructions : in array(0 to 15) of std_logic_vector(15 downto 0);
instruction_address : in std_logic_vector(3 downto 0);
clk : in std_logic;
instruction_out : out std_logic_vector(15 downto 0)
);
end instruction_buffer;
I've tried doing like this as well, but then I get syntax errors in my entity port mapping telling me that std_logic_vector
is an unknown type. I swear, VHDL's syntax errors are less meaningful than C haha
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
package instructionBuffer is
type instructionBuffer is array(0 to 15) of std_logic_vector (15 downto 0);
end package instructionBuffer;
entity instruction_buffer is
port
(
instruction_address : in std_logic_vector(3 downto 0);
clk : in std_logic;
instruction_out : out std_logic_vector(15 downto 0)
);
end instruction_buffer;
There is no need to split into two files, simply put all code into one file. You can also use generics inside your package for scalability:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
package instruction_buffer_type is
constant INSTRUCTION_BUFFER_ADDRESS : integer := 4; --bits wide
constant INSTRUCTION_BUFFER_DATA : integer := 16; --bits wide
type instructionBuffer is array(0 to 2**INSTRUCTION_BUFFER_ADDRESS -1) of std_logic_vector (INSTRUCTION_BUFFER_DATA -1 downto 0);
end package instruction_buffer_type;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;
use work.instruction_buffer_type.all;
entity instruction_buffer is
port
(
instruction_address : in std_logic_vector(INSTRUCTION_BUFFER_ADDRESS-1 downto 0);
instructions : in instructionBuffer;
clk : in std_logic;
instruction_out : out std_logic_vector(INSTRUCTION_BUFFER_DATA-1 downto 0)
);
end instruction_buffer;