Top "Hdl" questions

Using case statement and if-else at the same time?

I am trying to write Verilog HDL behavioral description of the machine specified in the state diagram below. I am …

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Conversion from numeric_std unsigned to std_logic_vector in vhdl

I have a question related to conversion from numeric_std to std_logic_vector. I am using moving average filter …

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BCD Adder in Verilog

I am trying to write a BCD Adder in Verilog, but I am having trouble with one of the modules. …

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4 bit adder-subtractor in verilog

I am writing verilog code for 4 bit adder subtractor. I am using structural design. At first I have written verilog …

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How do I convert a number to two's complement in verilog?

I am trying to design a 4-bit adder subtracter in verilog. This is only the second thing I have ever …

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not a valid l-value - verilog compiler error

module fronter ( arc, length, clinic ) ; input [7:0] arc; output reg [7:0] length ; input [1:0] clinic; input en0, en1, en2, en3; // 11 // clock generator is …

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What are the best practices for Hardware Description Languages (Verilog, VHDL etc.)

What best practices should be observed when implementing HDL code? What are the commonalities and differences when compared to more …

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What to use to compile and simulate Verilog programs on Mac OS X 10.6.8?

I am required to simulate Verilog programs as part of my syllabus. But, my college uses Xilinx ISE, and it …

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Seven Segment Multiplexing on Basys2

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four …

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How to break always block in Verilog?

I am trying to simulate a simple MIPS processor using behavior code in Verilog. I have finished writing the code …

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