Popular "fpga" questions | Page 4

I am having trouble initializing the contents of an inferred ram in Verilog. The code for the ram is as …

verilog fpga xilinx vivado

I am having a problem with using GHDL (http://ghdl.readthedocs.io/en/latest/) to simulate my VHDL design. So, …

vhdl fpga hdl ghdl

I keep hearing mostly from electrical engineers that C is used for fpga work. What about C++? Are there any …

c++ c fpga

I want to do project on image processing. i want to know if i want to implement this project on …

matlab opencv image-processing fpga

I'm trying to learn VHDL programming with some books and an Altera DE1 development kit from Terasic. The issue here …

vhdl fpga vga

This must be the most common problem among people new to VHDL, but I don't see what I'm doing wrong …

vhdl fpga intel-fpga

I'm very new to VHDL and XILINX ISE. I use the version 13.2 for Xilinx ISE. I want to design a …

vhdl fpga xilinx spartan

Below is the code that I am running. My question is why doesn't the 3rd wait until trigger in modelsim? …

vhdl fpga modelsim

In Vivado I succesfully made a simple blockdiagram to control the LEDs of my Zybo board. I can observe that …

fpga xilinx zynq vivado

is there any function in VHDL which is used to get current simulation time at which a process is running? …

vhdl fpga

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