Top "Fpga" questions

Incrementing a counter variable in verilog: combinational or sequential

I am implementing an FSM controller for a datapath circuit. The controller increments a counter internally. When I simulated the …

hardware verilog fpga sequential

VHDL: creating a very slow clock pulse based on a very fast clock

(I'd post this in EE but it seems there are far more VHDL questions here...) Background: I'm using the Xilinx …

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Triggering signal on both edges of the clock

Design requires a signal to be activated at specific circumstance on rising edge of the clock, and deactivated at another …

verilog clock fpga

Open-source field-programmable gate array (FPGA) development tools

I want to pick up FPGA programming. I've heard all types of horror stories of proprietary tools. Is there any …

fpga toolchain

How to interface a vga monitor to fpga using verilog?

I am using virtex - 5 fpga board and i am new in working with fpga board please suggest me any …

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Seven Segment Multiplexing on Basys2

this is my first post so I hope I'm doing this correctly. I'm trying to output a "4 3 2 1" on a four …

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Relation between LUTs, logic cell, logic elements, system gates

My question is related to difference and relationship between these terminology: LUTs Logic Cell Logic Elements(LE) System Gates I …

fpga

How to launch Xilinx ISE Web Pack under Ubuntu?

I've downloaded and successfully installed Xilinx ISE Web Pack 14.4 on Ubuntu 12.10 although I'm unable to launch it.

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VHDL - Incrementing Register Value on Push Button Event

I am very new to VHDL and am trying to figure out how to do something fairly basic on an …

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When to use VHDL library std_logic_unsigned and numeric_std?

I use VHDL-200X in ISE.I always use data type like std_logic_vector,std_logic,integer,boolean and …

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