Top "System-verilog" questions

Printing packed structs in System Verilog

I have a packed struct defined as shown below typedef struct packed { logic bit1; logic [7:0] byte1; } MyPackedStruct; MyPackedStruct myPackedStruct; Is …

printing struct verilog system-verilog packed

Can I set an enum with its numerical value?

I want to set an enum with the numerical value. Is the following code legal for SystemVerilog? `define DEC_ADDR 32…

enums system-verilog

What is the point of a "plain" begin-end block?

I'm reading some third party Verilog, and found this: function [31:0] factorial; input [3:0] operand; reg [3:0] index; begin factorial = operand ? 1 : 0; for(index = 2; …

verilog system-verilog

how to use assertoff from test to disable assertion in side uvm object

I am looking for way to disable assert in side uvm component for certain test. Below simple code represent my …

system-verilog uvm system-verilog-assertions

How can I use foreach and fork together to do something in parallel?

This question is not UVM specific but the example that I am working on is UVM related. I have an …

foreach fork system-verilog uvm

How to use verilog $deposit with indexes

How can $deposit be used when the path includes the index from the generate loop. When I try: for(int …

verilog system-verilog register-transfer-level

Combinational logic "IF" and "assign" statement in systemverilog

I found a very strange behaviour when design my ALU, hope someone can have a look it and tell me …

system-verilog alu

How to print the whole queue/array with UVM utility functions?

For UVM objects using `uvm_field_queue_int utility macro, UVM does not print out the whole queue when calling …

printing queue system-verilog uvm

SystemVerilog: How to connect C function using DPI call in VCS simulator?

I have the following files: C file with functions: // funcs.c #include <stdio.h> void something() { printf("something\…

c system-verilog synopsys-vcs system-verilog-dpi

Verilog multiple drivers

I'm trying to make BCD Counter using Verilog that will be connected to 7-segment decoder.After I synthesize it, the …

verilog xilinx system-verilog bcd