Object is used but not declared?

vhdl quartus
walidsarkis picture walidsarkis · May 29, 2015 · Viewed 10.8k times · Source

I have the following VHDL code, its a entity of a project:

library ieee;
use ieee.std_logic_1164.all;
library work;
use work.typedef.all;

entity uc is
    port(faaaa: in std_logic_vector(15 downto 0);
          phi: in std_logic;
          isDirect,isRam,jmp,store,NarOut,arpOut:out std_logic);
    end entity uc;

architecture b8 of ua is
    signal   instt : std_logic_vector(15 downto 0);
    signal bit7: std_logic;
        begin
            bit7<='0';
            instt <= faaaa;
            ....
            process(phi) is
            ....
            end process;
end architecture b8;

The error says that:

object "faaaa" is used but not declared

What am I doing wrong here?

Answer

scary_jeff picture scary_jeff · May 29, 2015

Your entity is called uc, but the architecture b8 is of ua.

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