How do I make Quartus II compile faster
I'm using Altera Quartus 2 to do a custom 8 bit processor and it takes forever to compile on my laptop. I'm only using simulations and making my processor in schematic (block diagram) and VHDL. Right now it takes around 10 minutes to compile, which is a pain since I'm more on the debugging phase of the project where I have to fix up the internal timing and make lots of very little changes to see what happens.
I'm not actually putting it on a FPGA, so do I need the compiling phases of "fitter" and "assembler"?
Can I change the contents of a memory file of one lpm_ram_dq and test it in simulation without recompiling?
In summary anyone knows how to make it compile faster?
Answer
Some useful flags to make Quartus synthesize faster if you don't care about fully optimizing your results and just want to get a pessimistic estimate or do comparisons.
set_global_assignment -name PHYSICAL_SYNTHESIS_EFFORT FAST
Specifies the amount of effort, in terms of compile time, physical synthesis should use. Fast uses less compile time but may reduce the performance gain that physical synthesis is able to achieve.
set_global_assignment -name FITTER_EFFORT FAST_FIT
Fast Fit decreases optimization effort to reduce compilation time, which may degrade design performance.
And instead of execute_flow -compile, use:
execute_flow -implement
Option to run compilation up to route stage and skipping all time intensive algorithms after.
In a meeting with Intel/Altera engineers, using -implement this was ball-parked to be about 20% faster than -compile, and came recommended when iterating on timing-closure results.
You could also try the following:
set_global_assignment -name SYNTHESIS_EFFORT FAST
Note: This has the caveat below, although I tend to see overall faster runs in some designs.
When set to Fast, some steps are omitted to accomplish synthesis more quickly; however, there may be some performance and resource cost. Altera recommends setting this option to Fast only when running an early timing estimate. Running a "fast" synthesis produces a netlist that is slightly harder for the Fitter to route, thus making the overall fitting process slower, which negates any performance increases achieved as a result of the "fast" synthesis.
Edit:
The below settings will punish your timing, but they can also help with compile time significantly, particularly on newer Stratix 10/Agilex designs:
set_global_assignment -name OPTIMIZATION_MODE "AGGRESSIVE COMPILE TIME"
set_global_assignment -name ALLOW_REGISTER_RETIMING "OFF"
set_global_assignment -name HYPER_RETIMER_FAST_FORWARD "OFF"
And you can also turn off timing analysis with the below:
set_global_assignment -name TIMEQUEST_MULTICORNER_ANALYSIS "OFF"