Error (10170): Verilog HDL syntax error at filename near text "input"; expecting ";"

verilog quartus
user3561441 picture user3561441 · Apr 22, 2014 · Viewed 9.2k times · Source

Working with 2014 version of Quartus II software (web edition), I receive the error 10170 when compiling the following code:

module shifter16 (A, H_sel, H)
input [15:0]A;
input H_sel;
output [15:0]H;
reg [15:0] H;
always @ (A or H_sel)
begin
    if (H_sel)
        H={A[14:0],1'b0};
    else
        H={A[15],A[15:1]};
end
endmodule

Error received:

Error (10170): Verilog HDL syntax error at shifter16.v(2) near text "input"; expecting ";"

Answer

Ari picture Ari · Apr 22, 2014

You need a semicolon at the end of the first line:

module shifter16 (A, H_sel, H);

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