In Verilog, I'm trying to use $readmemb to read .txt file but it only loads xxxxx (dont cares) on memory
I need to load a memory with some data originally in binary. I read that $readmemb can be use for this, and there is even a method to make synthesizable.
So, I created another module named RAM_IN (which is not the testbench module) and "connected" to the top module.
Before knowing about $readmemb, I was using this code:
initial
begin
in_ram [0] <= 32'b11111111_000000000000000000000000;
in_ram [1] <= 32'b10010111_000000000000000000000000;
in_ram [2] <= 32'b00110110_000000000000000000000000;
in_ram [3] <= 32'b00111110_000000000000000000000000;
in_ram [4] <= 32'b00111111_000000000000000000000000;
in_ram [5] <= 32'b00111110_000000000000000000000000;
end
But its too tiring for me to write 100 numbers like this, so implemented $readmemb like this:
module RAM_IN (pix_val, indx);
input [0:5] indx;
output [31:0] pix_val;
reg [31:0] pix_val;
reg [31:0] in_ram [0:4];
always @ (indx)
pix_val = in_ram [indx];
initial
begin
$readmemb("in_ram.txt", in_ram);
end
The purpose of reading this file, is to initially load 100 binary values (wich simulate the pixel intensity of a 10x10 image) one by one into the top module (which is going to process and spit a result later...)
I created a .txt file which looks content exactly like this
11111111000000000000000000000000
10010111000000000000000000000000
00110110000000000000000000000000
00111110000000000000000000000000
00111111000000000000000000000000
When I simulate, modelsim show me memory filled with xxxxxxxxxxxxxxxxx (dont care), it looks like isn't loading anything to the memory.
I don't know what I'm doing wrong. Likely isnt the dispossition of the numbers in the .txt file. Maybe is because I'm intending to load file with $readmemb in another module which is not testbench?
PD: The simulation of this process of filling the memory I'm doing only for practical purpose, the final intention is to put the Top module design into a full SoC which I think I will do using QSYS. But I'm very new at this so I'm still studying. Any help will be much appreciated!!!
Answer
Are you sure you run simulation?
Your code with TB:
module RAM_IN (pix_val, indx);
input [0:5] indx;
output [31:0] pix_val;
reg [31:0] pix_val;
reg [31:0] in_ram [0:4];
always @ (indx)
pix_val = in_ram [indx];
initial
begin
$readmemb("in_ram.txt", in_ram);
end
endmodule
module tb;
reg [0:5] indx;
wire [31:0] pix_val;
RAM_IN ram_in(pix_val, indx);
initial
begin
indx = 'b0;
$monitor ($realtime, " Read Data = %0b" ,pix_val);
repeat(4)
begin
#10;
indx = indx + 1'd1;
end
$finish;
end
endmodule
With same in_ram.txt.
Questasim:
QuestaSim-64 qverilog 10.4 Compiler 2014.12 Dec 2 2014
Start time: 18:27:01 on May 10,2016
qverilog me.v
-- Compiling module RAM_IN
-- Compiling module tb
Top level modules:
tb
Reading pref.tcl
# 10.4
# vsim -lib work tb -c -do "run -all; quit -f" -appendlog -l qverilog.log -vopt
# ** Note: (vsim-3812) Design is being optimized...
# // Questa Sim-64
# // Version 10.4 linux_x86_64 Dec 2 2014
# //
# // Copyright 1991-2014 Mentor Graphics Corporation
# // All Rights Reserved.
# //
# // THIS WORK CONTAINS TRADE SECRET AND PROPRIETARY INFORMATION
# // WHICH IS THE PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS
# // LICENSORS AND IS SUBJECT TO LICENSE TERMS.
# // THIS DOCUMENT CONTAINS TRADE SECRETS AND COMMERCIAL OR FINANCIAL
# // INFORMATION THAT ARE PRIVILEGED, CONFIDENTIAL, AND EXEMPT FROM
# // DISCLOSURE UNDER THE FREEDOM OF INFORMATION ACT, 5 U.S.C. SECTION 552.
# // FURTHERMORE, THIS INFORMATION IS PROHIBITED FROM DISCLOSURE UNDER
# // THE TRADE SECRETS ACT, 18 U.S.C. SECTION 1905.
# //
# Loading work.tb(fast)
# run -all
# 0 Read Data = 11111111000000000000000000000000
# 10 Read Data = 10010111000000000000000000000000
# 20 Read Data = 110110000000000000000000000000
# 30 Read Data = 111110000000000000000000000000
# ** Note: $finish : me.v(34)
# Time: 40 ns Iteration: 0 Instance: /tb
# End time: 18:27:02 on May 10,2016, Elapsed time: 0:00:01
# Errors: 0, Warnings: 0
And Simulation:
