Net, which fans out, cannot be assigned more than one value

verilog quartus digital-design
J. Koushyar picture J. Koushyar · Nov 24, 2017 · Viewed 15.1k times · Source

I am trying to design an 8-bit multiplier based on 4-bit multiplier. so this is my code:

module _8bit_multiply(a, b, q);

input [7:0] a;
input [7:0] b;

output [15:0] q;

wire [7:0] q0;
wire [7:0] q1;
wire [11:0] q2;
wire [11:0] q3;
wire [7:0] x0;
wire [11:0] x1;
wire [7:0] sum0;
wire [12:0] sum1;
wire [12:0] sum2;
wire co0;
wire co1;
wire temp;

_4bit_multiply m1(a[3:0], b[3:0], q0);

assign q[3:0] = q0[3:0];
assign x0[3:0] = q0[7:4];

_4bit_multiply m2(a[7:4], b[3:0], q1);

nbit_adder s1(x0, q1, 0, sum0, co0);

_4bit_multiply m3(a[3:0], b[7:4], q2);
_4bit_multiply m4(a[7:4], b[7:4], x1);

assign q3[11:4] = x1[7:0];

nbit_adder s2(q2, q3, 0, sum1, co1);

nbit_adder s3(sum0, sum1, co0, sum2, temp);
nbit_adder s4(sum2, 0, co1, sum2, temp);

assign q[15:4] = sum2[12:0];

endmodule

then I get this error:

Error (12014): Net "sum2[11]", which fans out to "q[15]", cannot be assigned more than one value

Error (12015): Net is fed by "nbit_adder:s3|s[11]" Error (12015):

Net is fed by "nbit_adder:s4|s[11]"

And more than like this. what should I do ?

Answer

Charles Clayton picture Charles Clayton · Nov 26, 2017

The same variable is the output of multiple modules in your code. Basically you're doing this:

assign sum2 = 1;
assign sum2 = 0;

So Quartus doesn't know what to do.

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