Testbench for T Flip Flop using D Flip Flop in VHDL

Question

I have VHDL codes that of a D Flip Flop, and a T Flip Flop that uses it structurally: it consists of a DFF with D input being T Xored with Q, a clock. But my simulation gives me a waveform that has an output of only a red straight line 'U'. I think it is because of the feedback from Q to D, and is uninitialized at the beginning. But I don't know how to write it otherwise. This is the code:

--This is the DFF:

    library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end d_flip_flop;

architecture d_flip_flop_arc of d_flip_flop is    
begin

    dff : process (din,clk,reset) is
    begin
        if (reset='1') then
            dout <= '0';
        elsif (rising_edge (clk)) then
            dout <= din;
        end if;
    end process dff;


end d_flip_flop_arc;

--TFF:

    library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity tff_using_dff is
     port(
         clk : in STD_LOGIC;
         t : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end tff_using_dff;

architecture tff_using_dff_arc of tff_using_dff is    

component d_flip_flop is
     port(
         clk : in STD_LOGIC;
         din : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end component d_flip_flop;

signal ip : std_logic;
signal op : std_logic;    

begin

    ip <= op xor t ;
    u0 : d_flip_flop port map (clk => clk,
                            din => ip,
                            reset => reset,
                            dout => op);

    dout <= op;


end tff_using_dff_arc;

--and current testbench:

 library IEEE;
use IEEE.STD_LOGIC_1164.all;

entity T_FF_tb is
end T_FF_tb;

architecture T_FF_tb of T_FF_tb is
component tff_using_dff is 
     port(
         clk : in STD_LOGIC;
         t : in STD_LOGIC;
         reset : in STD_LOGIC;
         dout : out STD_LOGIC
         );
end component;

signal clk,t,reset: std_logic:='0';
signal dout: std_logic:='0';
begin
U0: tff_using_dff port map(clk,t,reset,dout);
clk<=not clk after 5 ns;
t<= not t after 30 ns;

end T_FF_tb;

Answer 1

Your 'U' is caused by the output of the D flip flop being used in a combinatorial expression without being reset to a known state.

The simplest way to get the D flip flop buried in the T flip flop entity reset to a known would be to add a second process to the test bench along the lines:

RESET_PROC:
    process
    begin
        wait for 5 ns;
        reset <= '1';
        wait for 5 ns;
        reset <= '0';
        wait;
    end process;