What is the purpose of the `std_logic` enumerated type in VHDL?

vhdl digital
newprint picture newprint · Sep 20, 2012 · Viewed 13.1k times · Source

What is the purpose of the std_logic enumerated type?

'U': uninitialized. This signal hasn't been set yet.
'X': unknown. Impossible to determine this value/result.
'0': logic 0
'1': logic 1
'Z': High Impedance
'W': Weak signal, can't tell if it should be 0 or 1.
'L': Weak signal that should probably go to 0
'H': Weak signal that should probably go to 1
'-': Don't care.

Answer

BennyBarns picture BennyBarns · Sep 20, 2012
  • 'X' usually is caused by two statements driving the same signal in opposite directions,i.e., '0' and '1'
  • 'Z' is used to build a tri stated output/input
  • 'L' and 'H' are used to model a pulldown or pullup respectively
  • '-' is used in comparisons when you don't care about certain bits in a vector

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