What is the difference between elseif and elsif in VHDL

vhdl fpga digital
Jivan picture Jivan · Sep 2, 2012 · Viewed 10.4k times · Source

Currently, I've been involved in FPGA design techniques using Xilinix. While solving design problems, I repeatedly found the use of elseif and elsif in if-chain almost for similar statements.

elsif(clk'event and clk='1') then
                 pr_state<=nx_state;

and

elseif S1=’0’ and  S0=’1’ then
     Z <= B;

My problem is- what's the difference between these two constructs? Are they similar? I've gone through D.L. Perry's VHDL book and other online VHDL tutorials' sites but can't find solution.Thanks in advance!

Answer

BennyBarns picture BennyBarns · Sep 3, 2012

As you can see here
http://tams-www.informatik.uni-hamburg.de/vhdl/tools/grammar/vhdl93-bnf.html
elseif is not a valid keyword in vhdl. So if it is recognized, then some tool vendor wanted to do you a favour... I would guess that you actually saw else if, as pointed out above

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