number of ones in array

verilog hdl dataflow
Omar Sherif picture Omar Sherif · Oct 31, 2013 · Viewed 8.7k times · Source

I am trying to count the number of ones in a 4-bit binary number in Verilog, but my output is unexpected. I've tried several approaches; this is the one I think should work, but it doesn't.

module ones(one,in);
input [3:0]in;
output [1:0]one;

assign one = 2'b00; 
assign one = one+in[3]+in[2]+in[1]+in[0] ;

endmodule

Answer

N8TRO picture N8TRO · Oct 31, 2013

First, you can't assign the variable twice.

Second, your range is off, 2 bits can only go from 0 to 3. You need a 3 bit output to count up to 4.

This is more like what you need:

module ones(
  output wire [2:0] one,
  input wire [3:0] in
);

assign one = in[3]+in[2]+in[1]+in[0] ;

endmodule

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