Difference between Synchronous and Asynchronous reset in Flip Flops

verilog flip-flop
chitranna picture chitranna · Apr 2, 2013 · Viewed 25.9k times · Source 
always @ (posedge clk or negedge reset )
begin
//Asynchrous FF
end


always @(posedge clk)
begin
if (reset)
// Synchronous FF
end

What is the difference in the following implementations ? I mean in terms of number of size of the FF . Why and How are they synthesized by the Synthesizer?

Answer

Brian Magnuson picture Brian Magnuson · Apr 2, 2013

An asynchronous reset implies that you have a FF in your library that actually has a async clear (or async set) input. These tend to be a little larger than FFs that do not have these inputs, but this will vary depending on your libraries. These function such that as soon as the rest signal is asserted the Q of the FF will assume the reset state.

A synchronous reset will be implemented by including the reset signal in the fan-in cone of the D input of the FF. This means that when reset is asserted it will not take effect until the next active edge of your clock.

Precisely when you should use one over the other is an expansive subject.

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