What does "Illegal reference to net error" mean?

verilog flip-flop
James Aflred picture James Aflred · Mar 3, 2013 · Viewed 27.3k times · Source

I wrote this code for a T Flipflop. The output is toggled at every 11th clk. The program is giving me this error:

Illegal reference to net "clkDivider"

What does this error mean? What is causing it?

Here is the code:

module TFF(clkDivider,clk,reset,q);

input clk,reset;
input [3:0]clkDivider;
output reg q;

always @(posedge clk or negedge reset)
begin
   if(~reset==0)
   begin
      q=0;
      clkDivider<=0;
   end
   else
      if(clkDivider==11)
      begin
         q=1;
         clkDivider<=0;
      end
      else
         clkDivider<=clkDivider+1;
end

endmodule

Answer

toolic picture toolic · Mar 3, 2013

You should not assign values to a module input signal. Try:

output reg [3:0] clkDivider;

Also, you probably should use nonblocking assignments to q, such as:

q <= 0;

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