$readmemh $writememh related resources

hardware verilog
Alphaneo picture Alphaneo · Mar 10, 2009 · Viewed 59.4k times · Source

Suddenly, I am made to look into some verilog testbench code which heavily uses $readmemh, and $writememh. I understood that it basically read to memory and write to memory. I will be happy if you can point to some resources related to those routines. PS: I searched in google for no success. (I am very ... very new to Verilog)

Answer

danielpoe picture danielpoe · Mar 10, 2009

I agree its not too easy to find something about readmem/writemem. You can find a little bit here: https://www.fullchipdesign.com/readmemh.htm

Anyway there is not too much to say about these functions, the syntax is:

$readmem[hb]("File", ArrayName, StartAddr, EndAddr)
$writemem[hb]("File", ArrayName, StartAddr, EndAddr)

Verilog is very picky about the file format, the number of bit in the text file have to match the number of bits in the array.

I recommend you play around a little bit by defining an array, filling it up with data write it out with writememh/writememb and print it out afterwards.

Something like this should get you started (not tried out!).

integer i;
reg [7:0] memory [0:15]; // 8 bit memory with 16 entries

initial begin
    for (i=0; i<16; i++) begin
        memory[i] = i;
    end
    $writememb("memory_binary.txt", memory);
    $writememh("memory_hex.txt", memory);
end

Cheers!

Related questions

If statement and assigning wires in Verilog

I am trying to figure out the basics of assigning wires based on combinational logic. I have: wire val; wire x; wire a; wire b; always @* begin if(val == 00) //I want to assign x = a if(val == 01) //I want to …

Read More
Tool for drawing timing diagrams

Recently I am working with a hardware design group developing an ASIC. And I am drawing a lot of timing diagrams for which I am using Microsoft Excel, as it is easy to import into Word document. But, things are …

Read More
Incrementing a counter variable in verilog: combinational or sequential

I am implementing an FSM controller for a datapath circuit. The controller increments a counter internally. When I simulated the program below, the counter was never updated. reg[3:0] counter; //incrementing counter in combinational block counter = counter + 4'b1; However, on creating …

Read More