I have a question related to conversion from numeric_std to std_logic_vector. I am using moving average filter code that I saw online and filtering my ADC values to stable the values.
The filter package code is:
library …
I am supposed to create 4 bit full adder verilog code in vivado.But when I try to test in the simulation.It give me z and x output.Which part of code I have to change to get an output …