For a class, I was asked to write a VHDL procedure that takes two integer inputs A and B and replaces A with A+B and B with A-B. I wrote the following program and testbench. It completes implementation and the Behavioral Syntax check but it will not simulate. Although I get no errors, I do get some warnings stating that A and B are in combinational feedback loops. Can someone shed some light on what the problem may be?
Module:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
entity Problem2 is
Port ( A : inout integer;
B : inout integer);
end Problem2;
architecture Behavioral of Problem2 is
procedure AB (signal A,B: inout integer) is
begin
A<=A+B after 20 ns;
B<=A-B after 30 ns;
end AB;
begin
AB(A=>A, B=>B);
end Behavioral;
TestBench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY Problem2_test IS
END Problem2_test;
ARCHITECTURE behavior OF Problem2_test IS
-- Component Declaration for the Unit Under Test (UUT)
COMPONENT Problem2
PORT(
A : INOUT integer;
B : INOUT integer
);
END COMPONENT;
--BiDirs
signal A : integer;
signal B : integer;
-- No clocks detected in port list. Replace <clock> below with
-- appropriate port name
BEGIN
-- Instantiate the Unit Under Test (UUT)
uut: Problem2 PORT MAP (
A => A,
B => B
);
ABproc: process is
begin
A<=25;
B<=22;
wait;
end process;
END;
Answer
The problem is:
- Your component writes to it's own inputs. This is the equivalent of an infinite loop. The reason you've done this is because ....
- The description of the problem doesn't make sense.
I was asked to write a VHDL procedure that takes two integer inputs A and B...
Fine
...and replaces A with...
What?!
You can't replace A (or B) because you'll get this problem. You could write a procedure that takes two integer inputs, and gives two integer outputs. Those outputs could then feed some registers which then feed the input, but there has to be a register there to break the combinatorial feedback loop.