Why can't I increment this `std_logic_vector`

vhdl
Marty picture Marty · May 12, 2009 · Viewed 97.6k times · Source

What's going on here? Why am I getting an 'operator argument type mismatch', and what can I do to fix it?

--
-- 32-bit counter with enable and async reset
--
architecture synthesis1 of counter_32bit is    
signal nextvalue : std_logic_vector ( 31 downto 0 );    
begin

  --
  -- combo
  --
  nextvalue <= value + 1; -- here

  --
  -- sequential
  --
  ff:process( clk, rst )
  begin

    if( rst = '1' ) then
      value <= 0; -- and here...
    elsif( clk'event and ( clk ='1' ) ) then
      if( ena = '1' ) then
         value <= nextvalue;
      end if;
    end if;

  end process ff;    

end synthesis1;

Thanks

Answer

danielpoe picture danielpoe · May 13, 2009

you can't increment std_logic directly, you need to convert it to unsigned and the result back to std_logic_vector using the numeric_std package. 

use ieee.numeric_std.all
...
nextvalue <= std_logic_vector( unsigned(value) + 1 );

See How Do Perform STD_LOGIC_VECTOR Addition Using IEEE.NUMERIC_STD for example.

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