downto vs. to in VHDL

vhdl
ZacAttack picture ZacAttack · Oct 4, 2011 · Viewed 57.7k times · Source

I'm not sure I understand the difference between 'downto' vs. 'to' in vhdl.

I've seen some online explanations, but I still don't think I understand. Can anyone lay it out for me?

Answer

vipin picture vipin · Oct 4, 2011

If you take a processor, for Little endian systems we can use "downto" and for Bigendian systems we use "to".

For example, 

signal t1 : std_logic_vector(7 downto 0); --7th bit is MSB and 0th bit is LSB here.

and,

signal t2 : std_logic_vector(0 to 7); --0th bit is MSB and 7th bit is LSB here.

You are free to use both types of representations, just have to make sure that other parts of the design are written accordingly.

This post says something different:

"The term big endian (or little endian) designates the byte order in byte oriented processors and doesn't fit for VHDL bit vectors. The technical term is ascending and descending array range. Predefined numerical types like signed and unsigned are restricted to descending ranges by convention."

So, this answer can be confusing...

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