4 bit magnitude comparator VHDL

vhdl comparator magnitude
rockstiff picture rockstiff · Jun 27, 2015 · Viewed 9.9k times · Source

I have to make a 4bit magnitude comparator in VHDL with only concurrent statements (no if/else or case/when).

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Exercise is
port (  A : in std_logic_vector (3 downto 0);
        B : in std_logic_vector (3 downto 0);
        Ag : out std_logic;
        Bg : out std_logic;
        AeqB: out std_logic
       );   
end Exercise;

architecture Comparator of Exercise is

begin
    Ag <= '1'when (A>B) else '0'; 
    Bg <= '1' when (B>A) else '0';  --Problem: Here if i sumulate B="ZZZZ", Bg is 1, asi if B>A 
    AeqB<= '1' when (A=B) else '0'; 
end Comparator;

The problem is that i need to take in count all the other values of std_logic (U,X,Z,W,L,H,-), i know there is the others but cant figure it out how to make the comparator with with/select statement.

Thanks

Answer

scary_jeff picture scary_jeff · Jun 29, 2015

In general you can 'convert' the various values that std_logic can take into either 0 or 1 using the to_01 function. I think it's in package numeric_std.

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