clk'event vs rising_edge()

vhdl
Diego Herranz picture Diego Herranz · Mar 4, 2013 · Viewed 116.9k times · Source

I had always used this for detecting a rising edge:

if (clk'event and clk='1') then

but this can also be used:

if rising_edge(clk) then

Reading this post, rising_edge(clk) is recommended, but there is also a comment indicating that rising_edge(clk) could lead to wrong behaviour.

I can't decide which one to choose for the future, going on with (clk'event and clk='1') or adopting rising_edge(clk).

Any real-world expereince on these two? Any preferences?

Thanks!

Answer

Bill Lynch picture Bill Lynch · Mar 4, 2013

rising_edge is defined as:

FUNCTION rising_edge  (SIGNAL s : std_ulogic) RETURN BOOLEAN IS
BEGIN
    RETURN (s'EVENT AND (To_X01(s) = '1') AND
                        (To_X01(s'LAST_VALUE) = '0'));
END;

FUNCTION To_X01  ( s : std_ulogic ) RETURN  X01 IS
BEGIN
    RETURN (cvt_to_x01(s));
END;

CONSTANT cvt_to_x01 : logic_x01_table := (
                     'X',  -- 'U'
                     'X',  -- 'X'
                     '0',  -- '0'
                     '1',  -- '1'
                     'X',  -- 'Z'
                     'X',  -- 'W'
                     '0',  -- 'L'
                     '1',  -- 'H'
                     'X'   -- '-'
                    );

If your clock only goes from 0 to 1, and from 1 to 0, then rising_edge will produce identical code. Otherwise, you can interpret the difference.

Personally, my clocks only go from 0 to 1 and vice versa. I find rising_edge(clk) to be more descriptive than the (clk'event and clk = '1') variant.

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