What is the difference between using an initial block vs initializing a reg variable in systemverilog?

verilog simulation system-verilog
supernun picture supernun · Jul 18, 2016 · Viewed 13.8k times · Source

What is the difference between the following two examples with regards to simulation?

A)

reg a;
initial a = 1'b0;

and

B)

reg a = 1'b0;

Is it different for logic variables?

Answer

dave_59 picture dave_59 · Jul 18, 2016

The difference is initialization as part of a variable declarations execute before any process started by any initial or always constructs. If you wrote:

bit clk;
initial clk = 1;
always #5 clk++;
always @(posedge clk) ...;

There is a race condition as to whether the @(posedge clk) gets triggered at time 0 or time 10. However with:

bit clk = 1;
always #5 clk++;
always @(posedge clk) ...;

There is no race with the above. The first posedge will come at 10 time units.

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