Setting Probes for SimVision in Verilog Code

verilog simulation cadence
Johannes picture Johannes · Feb 9, 2015 · Viewed 11.9k times · Source

I am working on simulations of verilog builded digital logic and need to restart a simulation very often to see the changes. I am using Cadence SimVision to review the waveforms.

Is there a way to write commands in verilog for the SimVision environment? I mean things like probes and Parameters.

Answer

Morgan picture Morgan · Feb 9, 2015

It is not Verilog but you can create a tcl file.

shm.tcl:

database -open waves -shm
probe -create your_top_level -depth all -all -shm -database waves
run 
exit

Now to run your simulation use:

irun -access +r testcase.sv -input shm.tcl

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