How to ignore output ports with port maps

port vhdl
paul23 picture paul23 · Oct 16, 2013 · Viewed 33.2k times · Source

Well often in VHDL I notice that a certain component has multiple output ports. Ie in one of our examples we were given the following component:

COMPONENT eight_bitadder
  PORT ( a, b: in std_logic_vector(7 downto 0); 
        f: in std_logic; 
        C: out std_logic_vector(7 downto 0); 
        o, z: out std_logic);
END COMPONENT;

Where z determines if the result is 0, and o triggers on overflow.

Now in my case I wish to use this adder, however the actual result is not of importance, rather I only wish to check if the result is "0". I could of course add a dummy signal and store the port to this signal, however that seems needlessly complicated, and might add extra components during synthesis?

Answer

Russell picture Russell · Oct 16, 2013

When you instantiate the component you can leave the output ports that you don't care about open. The only signal you care about below is "overflow".

EDIT: Note that the synthesis tools will optimize away any outputs that are not being used.

EIGHT_BITADDER_INST : eight_bitadder
  port map (
    a => a,
    b => b, 
    f => f, 
    c => open, 
    o => overflow,
    z => open
    );

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