Verilog 32-bit ALU with Overflow, Sign, and Zero Flags

Question

I have an assignment asking for creation of a module as described in the title. I need to add, subtract, AND, and XOR two inputs and set the necessary flags. The assignment wasn't 100% clear, but I'm assuming that the overflow flag will render everything else invalid so I don't need to worry about anything that goes over the 32-bit result. My problem comes with the zero and overflow flags, which never seem to get set no matter what I try. I've put together some methods I found online but I'm not sure if those methods are wrong or if I'm coding it wrong. Everything compiles and runs but my flags never set no matter what inputs I use. I've only taken one Verilog class and don't remember a lot of the constraints so any help would be appreciated.

module alu(clk, rst, CTRL, A, B, Overflow, Z_flag, Negative, d_out);

input wire clk , rst;
input wire [1:0] CTRL;
input wire signed [31:0] A, B;

output wire Negative;
output reg Z_flag;
output reg [1:0] Overflow;
output wire [31:0] d_out;
reg signed [32+32:0] Result;

assign Negative = Result[31]; // Negative Flag
assign d_out [31:0] = Result [31:0];

always@(posedge clk) 
begin
    if(!rst) 
    begin
        if(rst)
        begin
        Result [31:0] <= 0;
        end

        case(CTRL)      
        2'b00: 
        begin
            Result [32:0] <= {A[31], A [31:0]} + {B[31], B [31:0]}; // Add A + B
                 if(Result [32:31] == (2'b11 | 2'b10)) Overflow <= 1'b1;
            else Overflow <= 1'b0;
        end

        2'b01: 
        begin
            Result [32:0] <= {A[31], A [31:0]} - {B[31], B [31:0]}; // Subtract A - B
                 if((Result[32+32]) && (~Result [32+31:31] != 0)) Overflow <= 1'b1;
            else if ((~Result[32+32]) && (Result [32+31:31] != 0)) Overflow <= 1'b1;
                 else Overflow <= 1'b0;
        end

        2'b10: 
        begin
            Result [31:0] <= A [31:0] & B [31:0]; // Bitwise AND
        end

        2'b11:
        begin
            Result [31:0] <= A [31:0] ^ B [31:0]; // Bitwise XOR
        end
        endcase

        if (Result == "32h'00000000") Z_flag <= 1'b1; // Zero detection
        else Z_flag <= 1'b0;
    end
end

Here is my testbench:

module ALU_stimulus;


   reg clk;
   reg rst;
   reg [1:0] CTRL;
   reg [31:0] A;
   reg [31:0] B;


   wire Overflow;
   wire Z_flag;
   wire Negative;
   wire [31:0] d_out;


   alu uut (
       .clk(clk),
       .rst(rst),
       .CTRL(CTRL),
       .A(A),
       .B(B),
       .Overflow(Overflow),
       .Z_flag(Z_flag),
       .Negative(Negative),
       .d_out(d_out)
   );

   initial begin

   clk = 0;
   rst = 0;
   CTRL = 0;
   A = 0;
   B = 0;


   #100;
   clk=1'b1;
   A=32'h00000000;
   B=32'h00000000;
   rst=1'b0;
   CTRL=2'b00;
   #100;
   clk=1'b0;
   #100 $stop;

   end

endmodule

Answer 1

For ease of an example consider 4 bit values with 1 bit sign extension.

1+1 =2 ; No Overflow

0 0001; //1
0 0001; //1
0 0010; //2

7+7= 14; Overflow for 4 bit value max is 7

0 0111; //1
0 0111; //1
0 1110; //-2

-1+-1 = -2; No Underflow

1 1111 //-1
1 1111 //-1
1 1110 //-2

-8+-8 = -16 Underflow min value is -8

1 1000 //-8
1 1000 //-8
1 0000 // 0

Looking at the MSBs (sign extension and MSB) we can see :

00 => normal
01 => Overflow
10 => Underflow
11 => normal