Random number generation on Spartan-3E

Question

I need to generate pseudo-random numbers for my genetic algorithm on a Spartan-3E FPGA and i want to implement it in verilog: could you give me any pointers on this?

Answer 1

Of course the random generator by Adam is not synthesizable! You have to explicitly create an LFSR.

Following example might help. It is an 8-bit maximal LFSR

module lfsr(input clk, reset, en, output reg [7:0] q);
  always @(posedge clk or posedge reset) begin
    if (reset)
      q <= 8'd1; // can be anything except zero
    else if (en)
      q <= {q[6:0], q[7] ^ q[5] ^ q[4] ^ q[3]}; // polynomial for maximal LFSR
  end
endmodule;