The DMA for stm32F4 series has some advanced functions, could I ask for clarification here?
Concurrent stream: Can two streams transmit data at the same time? Since one byte transfer is allowed. If the bus width is 32bit, 4 concurrent transmission is possible. Btw, what is the width of the AHB bus for STM32?
FIFO mode: If concurrent transmission is not possible, I guess FIFO could be used here. FIFO would help to wait data ready from low speed peripherals to DMA without occupying the AHB bus. When a certain amount of data are ready, the chunk of data will be sent to memory together. Is my understanding correct?
Four-word depth 32 first-in, first-out memory buffers (FIFOs) per stream
What does that mean? How many data can be stored in the FIFO? 4 or 4*32?
Burst mode: What does actually burst mode do? It says in datasheet that 65535 data can be transmitted. What is the relation between 65535 with the burst mode?
Double buffer mode:
Double-buffer type transactions: double buffer transfers using two
memory pointers for the memory (while the DMA is reading/writing
from/to a buffer, the application can write/read to/from the other
buffer). -----From reference manual of STM32F4
My question is: During the DMA transmission, the AHB bus is not available for Cortex M4, how could the application read from the other buffer?
After doing some research, here is what I found, in case someone may need it.
concurrent stream: Not possible within one DMA. Possible to have DMA1, DMA2 running concurrently. E.g: F427 can do simultaneously:
FIFO is used to store data temporarily from Low speed device. When a certain amount of data have been accumulated, a burst could be sent, to save resource of AHB. Since when AHB is used by DMAC, it cannot be used by processor. FIFO has 4*32 bit size. It can be configured as 16*8 bit (16*0ne byte).