When to use the tick(') for Verilog array initialization?

arrays verilog system-verilog array-initialization
Victor Lyuboslavsky picture Victor Lyuboslavsky · Apr 18, 2014 · Viewed 33.9k times · Source

Array initialization can be done with or without the ':

int a[8] = '{0,1,2,3,4,5,6,7}; // Packed
int b[8] = {0,1,2,3,4,5,6,7};  // Unpacked

Is there a correct way, assuming the array uses an un-packable type like int, string, etc.? Both ways seem to work just fine.

Full code example on EDA Playground: http://www.edaplayground.com/x/3Tc

Answer

Qiu picture Qiu · Apr 19, 2014

Based on IEEE 1800-2009:

Array assignment patterns (1) have the advantage that they can be used to create assignment pattern expressions of selfdetermined type by prefixing the pattern with a type name. Furthermore, items in an assignment pattern can be replicated using syntax such as '{ n{element} }, and can be defaulted using the default: syntax. However, every element item in an array assignment pattern must be of the same type as the element type of the target array. By contrast, unpacked array concatenations (2) forbid replication, defaulting and explicit typing, but they offer the additional flexibility of composing an array value from an arbitrary mix of elements and arrays.

So:

int A3[1:3];
int A9[1:9];

A3 = '{1, 2, 3}; #legal
A9 = '{3{A3}};   #illegal
A9 = {A3, 4, 5, A3, 6}; #legal
A9 = '{9{1}}; #legal
A9 = {9{1}}; #illegal

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