How to set all the bits to be 0 in a two-dimensional array in Verilog?

Question

I've built a 8*2bits array to represent a piece of memory in Verilog

reg [1:0] m [0:7]

There is a reset signal for this memory and if reset is 1, all the bits in this memory should be reset to 0. But I don't know how to set all the bits of m in a concise way, because if there are hundreds thousands of bits in the memory, the following way is obviously unfeasible.

always@(posedge clk or posedge reset)
begin
  if (reset) 
    begin
      m[0]<=2'b00;
      m[1]<=2'b00;
      m[2]<=2'b00;
      m[3]<=2'b00;        
      m[4]<=2'b00;
      m[5]<=2'b00;
      m[6]<=2'b00;
      m[7]<=2'b00;
    end
  else
    ....
end

Answer 1

Use a for loop:

  integer i;
  always@(posedge clk or posedge reset)
  begin
    if (reset) 
      begin
        for (i=0; i<8; i=i+1) m[i] <= 2'b00;
      end
    else
      ....
  end

This is described in the IEEE Std 1800-2012 (Section 12.7.1 The for-loop, for example).