Verilog: How to instantiate a module
If I have a Verilog module 'top' and a verilog module 'subcomponent' how do I instantiate subcomponent in top?
top:
module top(
input clk,
input rst_n,
input enable,
input [9:0] data_rx_1,
input [9:0] data_rx_2,
output [9:0] data_tx_2
);
subcomponent:
module …