How to interpret blocking vs non blocking assignments in Verilog?

verilog system-verilog
infinitloop picture infinitloop · Jan 11, 2011 · Viewed 33.2k times · Source

I am a little confused about how blocking and non blocking assignments are interpreted when it comes to drawing a hardware diagram. Do we have to infer that a non blocking assignment gives us a register? Then according to this statement c <= a+b , c would be a register right, but not a and b? 

module add (input logic clock,  
output logic[7:0] f);   

logic[7:0] a, b, c;  

always_ff @(posedge clock)  
begin   
  a = b + c;   
  b = c + a;   
  c <= a + b;  
end   

assign f = c;  

endmodule

Answer

Jan Decaluwe picture Jan Decaluwe · Jan 23, 2011

The conventional Verilog wisdom has it all wrong. There is no problem with using blocking assignments for a local variable. However, you should never use blocking assignments for synchronous communication, as this is nondeterministic.

A non-blocking assignment within a clocked always block will always infer a flip-flop, as dictated by the semantics.

Whether a blocking assignment within a clocked always block infers a flip-flop or not depends entirely on how it is used. If it is possible that the variable is read before being assigned, a flip-flop will be inferred. Otherwise, this is like a temporary variable and it will result in some combinatorial logic.

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