Assigning values in Verilog: difference between assign, <= and =

verilog assign
dringx picture dringx · Dec 12, 2014 · Viewed 11.9k times · Source

I have just started learning Verilog and I've seen these three lines from different sources. I am confused about the difference between the three:

  1. c <= a&b
  2. assign c = ~a;
  3. c = 1'b0;

These lines seem to assign a value to c but what's the difference? Thanks.

Answer

chris picture chris · Dec 12, 2014

1) <=non-blocking and is performed on every positive edge of clock. these are evaluated in parallel so no guarantee of order. An example of this would be a register.

2) assign =continual assignment to wire outside an always statement. value of LHS is updated when RHS changes.

3) =blocking assignment, inside always statements enforces sequential order.

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