<= Assignment Operator in Verilog

verilog
biw picture biw · Nov 4, 2014 · Viewed 21.6k times · Source

What does the <= do in Verilog?

For example:

always @(posedge Clock) begin
   if (Clear) begin
      BCD1 <= 0;
      BCD0 <= 0;
   end
end

Answer

Emman picture Emman · Nov 4, 2014

"<=" in Verilog is called non-blocking assignment which brings a whole lot of difference than "=" which is called as blocking assignment because of scheduling events in any vendor based simulators.

It is Recommended to use non-blocking assignment for sequential logic and blocking assignment for combinational logic, only then it infers correct hardware logic during synthesis.

Non-blocking statements in sequential block will infer flip flop in actual hardware.

Always remember do not mix blocking and non-blocking in any sequential or combinational block.

During scheduling process of simulator:

There are four regions and order of execution of commands as follows

1) Active region
     --Blocking assignments
     --Evaluation of RHS of non-blocking assignments(NBA)
     --Continuous assignment
     --$display command
     --Evaluate input and output of primitives
2) Inactive region
     --#0 blocking assignments
3) NBA(non-blocking assignment update)
     --update LHS of non-blocking assignments (NBA)
4) Postponed
     --$monitor command
     --$strobe command

Using of blocking assignment "=" for two variable at the same time slot causes race condition

eg: Verilog code with race condition, 

always @(posedge Clock) 
   BCD0 = 0; // Usage of blocking statements should be avoided
always @(posedge Clock) 
   BCD1 = BCD0;

In order to avoid race condition use non-blocking statement "<="

eg: 

   always @(posedge Clock) 
       BCD0 <= 0; // Recommended to use NBA
    always @(posedge Clock) 
       BCD1 <= BCD0;

When this block is executed, there will be two events added to the non blocking assign update queue. Hence, it does the updation of BCD1 from BCD0 at the end of the time step.

Using Non-blocking "<=" assignment in continuous assignment statement is not allowed according to verilog LRM and will result in compilation error.

eg: 

assign BCD0 <= BCD1; //Results in compilation error

Only use NBA in procedural assignment statements, 

 - initial and
 - always blocks

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